The present invention relates to semiconductor devices and methods of fabrication therefor, and more particularly, semiconductor devices with recessed gate electrode portions and methods for forming the same.
An integrated circuit (IC) may include several metal oxide semiconductor (MOS) transistors. As ICs become more highly integrated, the scale of such MOS transistors may decrease. Therefore, there is a need for reducing problems arising from short channel effects for such small-scale MOS transistors.
A gate of a MOS transistor may be formed by a method wherein a gate insulator is formed on a semiconductor substrate and then a gate conductive layer is formed on the gate insulator and patterned. Source/drain regions may be formed by performing ion-implantation process after forming the gate electrode.
However, the gate formed by a conventional patterning process may have etch damage on sidewalls thereof, so that charge may inconstantly flow from the channel to the periphery of the gate and leakage of current may occur. Additionally, conventional methods may not be capable of forming a gate electrode having a shorter channel length than a resolution of a photolithography process. This may serve as a limit on operation speed and power consumption characteristics.
In order to solve problems due to etch damage and to improve characteristics of a semiconductor device, a T-shaped gate electrode formed by a damascene process has been introduced as shown, for example, in U.S. Pat. No. 6,255,202.
FIGS. 1 through 4 are cross-sectional views showing a conventional method for forming a T-shaped gate electrode. Referring to FIG. 1, an oxide layer 13 and a nitride layer 15 are sequentially formed on a semiconductor substrate 11. The nitride layer 15 is patterned using a photolithography process, thereby forming an initial groove 17 exposing the oxide layer 13. Referring to FIG. 2, spacers 19 are formed on sidewalls of the initial groove 17. The exposed oxide layer 13 is patterned using the spacers 19 as etch masks, thereby exposing the semiconductor substrate 11.
Referring to FIG. 3, the spacers 19 are removed to form a final groove 21. A gate oxide layer 23 is formed on the exposed semiconductor substrate 11, and the final groove 21 is filled with a conductive material, thereby forming a T-shaped gate electrode 25. Although not illustrated, the nitride layer 15 is removed and an ion-implantation process is performed to form source/drain regions (not shown) in a subsequent process.
In order to reduce problems arising from a short channel effect, source/drain regions are typically formed very shallowly. However, as semiconductor devices become increasingly highly integrated, it is generally more difficult to form source/drain regions very shallowly in a process of forming a T-shaped gate or a conventional gate. To address these problems, a process of forming a recessed gate electrode portion (or an elevated source/drain) has been introduced, as described, for example, in U.S. Pat. No. 6,303,448, which discloses a process for forming a recessed gate electrode portion (or an elevated source/drain).
FIGS. 5 through 7 are cross-sectional views showing a conventional method of forming a recessed gate electrode portion. Referring to FIG. 5, an oxide layer 53 and a nitride layer 55 are sequentially formed on a semiconductor substrate 51. The nitride layer 55, the oxide layer 53 and a part of the semiconductor substrate 51 are anisotropically dry-etched to form a groove 57. Referring to FIG. 6, a gate insulator 63 is formed on the surface of the etched semiconductor substrate 51 by a thermal oxidation process. Referring to FIG. 7, the groove 57 is filled with a conductive material, thereby forming a recessed gate electrode portion 65. Although not illustrated, the nitride layer 55 is removed and an ion-implantation process is performed to form source/drain regions in a subsequent process.
The conventional methods described above may have several problems. According to a conventional process of forming a T-shaped gate electrode, it may be difficult to form source/drain regions with shallow junctions. This may be because the channel typically is formed around a surface of a semiconductor substrate like a conventional gate process. Also, drain-induced barrier lowering DIBL may occur, which may cause a leakage current between the semiconductor substrate and a gate insulator at a lower voltage than a threshold voltage.
According to some conventional processes of forming a recessed gate electrode portion, a capacitance of a parasitic capacitor is increased due to overlap of gate electrode and source/drain. This is because the semiconductor substrate is partially etched to enlarge a contact area between the gate electrode and the semiconductor substrate and also a gate insulator of a thermal oxide is thinly conformally formed along an inner wall of a groove formed on the semiconductor substrate. Gate-induced drain leakage (GIDL) may be increased in a device fabricated in such a manner.